Math

Floating-point work, vectors, and SIMD-oriented examples with XMM registers.

XMM registers let one instruction work on several values at once. The important ideas are alignment, lane width, and the suffix that tells you whether an operation is scalar or packed.

Lay out aligned vectors

An XMM register is 128 bits, or 16 bytes. These declarations arrange four 32-bit integers, four 32-bit floats, or two 64-bit doubles in exactly that space. The aligned move instructions expect the address to be 16-byte aligned.

Lay out aligned vectors source/chapters/math.asm

align 16    ; misalignment will cause access violation
nums0 dword 1, 2, 3, 4    ; 128 bit aligned 4 x i32 vector
nums1 dword 1, 3, 5, 7    ; 128 bit aligned 4 x i32 vector
fnum0 real4 1.5, 2.4, 3.8, 3.141592    ; 128 bit aligned 4 x f32 vector
fnum1 real4 3.9, 1.6, 2.5, 8.23    ; 128 bit aligned 4 x f32 vector
dnum0 real8 1.5, 3.1415926535897932    ; 128 bit aligned 2 x f64 vector
dnum1 real8 1.5, 3.1415926535897932    ; 128 bit aligned 2 x f64 vector

Keep in mind: Match the data declaration, alignment, and instruction suffix.

Packed integer lanes

movdqa loads an aligned 128-bit integer vector. paddd and psubd then perform four independent 32-bit operations in parallel.

Packed integer lanes source/chapters/math.asm

    movdqa xmm0, xmmword ptr [nums0]    ; type coalescing data into xmm reg
    paddd xmm0, xmmword ptr [nums1]    ; packed integer add dword
    movdqa xmm1, xmmword ptr [nums1]    ; move double quadword aligned
    psubd xmm0, xmm1    ; packed integer subtract dword

Keep in mind: Packed arithmetic does not carry from one lane into the next.

Scalar floating-point operations

The ss suffix means scalar single precision: only the low 32-bit float participates. This is useful when you want SSE arithmetic without treating the register as a four-value vector.

Scalar floating-point operations source/chapters/math.asm

    movss xmm0, fnum0
    movss xmm1, fnum1

    addss xmm0, xmm1
    mulss xmm0, xmm1
    subss xmm0, xmm1
    divss xmm0, xmm1

Keep in mind: Scalar SSE instructions leave the upper lanes outside the calculation.

Packed float and double operations

ps means packed single precision and operates on four floats. pd means packed double precision and operates on two doubles.

Packed float and double operations source/chapters/math.asm

    movaps xmm0, xmmword ptr [fnum0]
    movaps xmm1, xmmword ptr [fnum1]
    divps xmm0, xmm1

    movapd xmm2, xmmword ptr [dnum0]
    movapd xmm3, xmmword ptr [dnum1]
    divpd xmm2, xmm3

Keep in mind: Read suffixes as part of the instruction: ps, pd, ss, and sd describe the lanes.

Keep these rules

XMM registers hold 128 bits divided into typed lanes.
Aligned moves require aligned storage.
Instruction suffixes distinguish scalar from packed work.